01ACTIVE
Low-Power OTA Design Study
A reproducible gm/ID-driven design flow for a two-stage operational transconductance amplifier, including sizing tables and PVT verification.
- PROCESS
- 180 nm CMOS
- TARGET
- 1.8 V
- TOOLS
- 65 µA
#gm-id#stability#pvt
OPEN ENGINEERING LOG
Projects
Longer-form design studies with constraints, trade-offs, simulations, and reproducible artifacts.
02DOCUMENTED
10-bit SAR ADC Behavioral Model
An architecture-level model for exploring capacitor mismatch, comparator noise, and code-density metrics before transistor implementation.
- PROCESS
- 10 bit
- TARGET
- 1 MS/s
- TOOLS
- Python + SPICE
#sar-adc#modeling#monte-carlo