Building a SAR ADC Error Budget Before Transistor Design

An error budget turns converter resolution into engineering constraints. Without one, block-level design tends to over-optimize one error source while silently ignoring another.

Start from the quantization scale

For an $N$-bit ADC with differential full-scale range $V_{FS}$,

$$V_{LSB} = \frac{V_{FS}}{2^N}.$$

The RMS quantization noise of an ideal converter is

$$\sigma_q = \frac{V_{LSB}}{\sqrt{12}}.$$

This provides a natural reference for sampling noise, comparator noise, DAC mismatch, and incomplete settling.

Allocate independent errors

If error sources are approximately independent, combine their RMS contributions by root-sum-square:

$$\sigma_{total} = \sqrt{\sigma_{sample}^2 + \sigma_{comp}^2 + \sigma_{settle}^2 + \sigma_{other}^2}.$$

Do not allocate the full allowable error to every block. Reserve margin for model uncertainty, parasitics, and mechanisms that the first behavioral model does not include.

Sampling capacitor

The sampled thermal noise is approximately $kT/C$. Setting its RMS value below the allocated sampling-noise target gives a lower bound on capacitance:

$$C \geq \frac{kT}{\sigma_{sample}^2}.$$

Mismatch and switching linearity may set a larger capacitor than noise does.

Behavioral model first

A compact behavioral model can sweep comparator noise, capacitor mismatch, and settling time across thousands of conversions. Use it to identify which constraint actually limits SNDR and DNL before committing to a transistor topology.

Sign-off questions

• Does the budget cover every state-dependent error?
• Are deterministic and random errors treated separately?
• Is there margin for extracted parasitics and reference disturbance?
• Are the verification metrics tied to the converter’s use case?

An error budget is valuable when it stays alive: update it as measured block performance replaces assumptions.